VHDL-Forum - Syntax

Wertzuweisung std_logic_vector

Wertzuweisung std_logic_vector

Ich möchte einem Signal mit 32Bit Länge einen Wert zuweisen mithilfe einer anderen Variablen, die kürzer ist (z.B. 24Bit). siehe unten:

------------------------------------------------------------------------------------
SIGNAL signal1 : std_logic_vector(31 DOWNTO 0);
SIGNAL signal2 : std_logic_vector(23 DOWNTO 0);

signal1 <= signal2;

-----------------------------------------------------------------------------------

Beim compilieren erscheint folgender Fehler:
"expression has 24 elements, but must have 32 elements".

->wie kann ich also dem Signal "signal1" den Wert von "signal2" zuweisen? Bzw. wie kann ich aus "signal2" ein 32Bit-Vektor erzeugen, der den selben Wert besitzt?

Re: Wertzuweisung std_logic_vector

Hallo Lukas,

------------------------------------------------------------------------------------
SIGNAL signal1 : std_logic_vector(31 DOWNTO 0);
SIGNAL signal2 : std_logic_vector(23 DOWNTO 0);

signal1 <= signal2;
-----------------------------------------------------------------------------------

Bei dieser Zuweisung weiß der Compiler nicht welche Bits des einen Vektors er welchem Bit im anderen Vektor zuordnen soll; das mußt Du explizit festlegen, z.B. so

signal1(23 downto 0) <= signal2;

Du könntest nämlich auch folgendes gemeint haben:

signal1(31 downto 8) <= signal2;

Soweit klar?

Grüße,
Jonatan

Re: Wertzuweisung std_logic_vector

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